Free Verilog Compiler
In the last few years, we have seen the rise of several stand-alone integrated development environments (IDEs) — a.k.a VHDL and Verilog code browsers.Borrowing the concepts from software IDEs (Borland, Visual Studio, etc) these IDEs provide direct feedback about the code, and integration with simulators and/or synthesis tools. This semester, I have a Hardware course which requires the use of Verilog. I Googled for some free Verilog IDEs in which I can write Verilog programs and also compile and run them (I think the right word is 'simulate', but forgive me, I'm still used to C!), but I didn't get anything. Verilog simulation and synthesis tool 0. Download Icarus Verilog for free. Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
@feddischson
Regarding vunit_defines.svh everything in it except CHECK_EQUAL can be considered part of the core functionality. The CHECK_EQUAL should be moved to a separate check library which together with other convenient check-functions. The core functionality might be possible to implement in pure Verilog and but the check library might be SystemVerilog-only. That way Verilog-only simulators can still use the test-automation features of VUnit without benefiting from convenient check-functions.
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The original Verilog simulator, Gateway Design's Verilog-XL was the first (and only, for a time) Verilog simulator to be qualified for ASIC (validation) sign-off. After its acquisition by Cadence Design Systems, Verilog-XL changed very little over the years, retaining an interpreted language engine, and freezing language-support at Verilog-1995. This page contains Verilog tutorial, Verilog Syntax, Verilog Quick Reference, PLI, modelling memory and FSM, Writing Testbenches in Verilog, Lot of Verilog Examples and Verilog in One Day Tutorial. GHDL is an open-source simulator for the VHDL language. GHDL allows you to compile and execute your VHDL code directly in your PC. GHDL fully supports the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partially the latest 2008 revision (well enough to support fixedgenericpkg or floatgenericpkg).
Free Verilog Compiler
Anyway why not ask icarus for improvements? It is open source after all. I made tons of bug/feature issues to GHDL before it finally could run VUnit.
Free System Verilog Compiler
@svenka3
Regarding the purpose of the core functionality setup and the pass/fail mechanism. Basically the Python part of VUnit sets a runner_cfg generic that is a string in a certain format that contains a number of fields such as the test case to run and the output path. This string needs to be parsed in setup for the HDL-part of VUnit to now which if run('test_name') if statement(s) it should go into. The pass/fail mechanism is through writing the $output_path/vunit_results file. A pass is when the simulation ends with the correct contents in vunit_results file and a fail is a (premature) simulation ending without the correct results written into vunit_results. Basically if the simulation ends before reaching cleanup it is considered a fail.